 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| semiconductor technical data multioutput power supply pin connections order this document from analog marketing rev. 2.5, 11/2002 44lead hsop dh suffix case 1291 44lead qfn fc suffix case 1310 (bottom view) gnd cantxd canl canrxd canh /poreset hrt /hreset /sleep /prereset n/c n/c cs vddl_fb di vddl_b sclk vddl_x do vdd3_3fb n/c vdd3_3 vref3 vpp vref2 vpp_en vddh vref1 vpre_s wakeup vpre regon vcomp vsen inv vkam_fb gnd vkam sw2g vign boot n/c n/c ka_vbat 1 54lead soicwep dwb suffix case 1377 sw1 sw1 sw1 sw1 sw1 vbat vbat vbat vbat vbat soicw 1 motorola analog integrated circuit device data
the 33394 is a multioutput power supply integrated circuit with high speed can transceiver. the ic incorporates a switching preregulator operating over a wide input voltage range from +4.0v to +26.5v (with transients up to 45v). the switching regulator has an internal 3.0a current limit and runs in both buck mode or boost mode to always supply a preregulated output followed by low drop out (ldo) regulators: vddh / 5.0v @ 400ma; vdd3_3 / 3.3v @ 120ma; vddl / 2.6v (user scalable between 3.3v 1.25v) @ 400ma typically, using an external npn pass transistor. the keep alive regulator vkam (scalable) @ 50ma; flash memory programming voltage vpp / 5.0v or 3.3v @ 150ma; three sensor supply outputs vref(1,2,3) / 5.0v (tracking vddh) @ 100ma each; and a switched battery output (vsen) to supply 125ma clamped to 17v. additional features include active reset circuitry watching vddh, vdd3_3, vddl and vkam, user selectable hardware reset timer (hrt), power sequencing circuitry guarantees the core supply voltages never exceed their limits or polarities during system power up and power down. a high speed can transceiver physical layer interfaces between the microcontroller cmos outputs and differential bus lines. the can driver is short circuit protected and tolerant of loss of battery or ground conditions. 33394 is designed specifically to meet the needs of modules, which use the mpc565 microcontroller, though it will also support others from the mpc5xx family of motorola microcontrollers. features: ? wide operating input voltage range: +4.0v to +26.5v (+45v transient). ? provides all regulated voltages for mpc5xx mcus and other ecu's logic and analog functions. ? accurate power up/down sequencing. ? provides necessary mcu support monitoring and failsafe support. ? provides three 5.0 v buffer supplies for internal & external (shortcircuit protected) sensors. ? includes stepdown/stepup switching regulator to provide supply voltages during different battery conditions. ? interfaces directly to standard 5.0v i/o for cmos microprocessors by means of serial peripheral interface. pin connections vbat vbat ka_vbat vign vkam sw1 sw1 sw1 boot sw2g gnd /sleep hrt canh canl gnd vkam_fb vsen regon wakeup vref1 vpp_en vpp vdd3_3 vdd3_3fb vddl_x vddl_b cantxd canrxd /poreset /hreset /prereset vddl_fb cs di sclk do vref3 vref2 vddh vpre_s vpre vcomp inv 1 vbat sw1 vbat sw1 ka_vbat sw1 vign boot vkam sw2g vkam_fb gnd vsen inv regon vcomp wakeup vpre vref1 vpre_s vpp_en vddh vpp vref2 vdd3_3 vref3 vdd3_3fb do vddl_x sclk vddl_b di vddl_fb cs /prereset /sleep /hreset hrt /poreset canh canrxd canl cantxd gnd 1 hsop qfn top view ? motorola, inc. 2002 this document contains information on a new product. specifications and information herein are subject to change without notice. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 2 motorola analog integrated circuit device data figure 1. 33394dh simplified block diagram and typical application can wakeup logic band gap reference standby control vref1 5.0 v 100 ma ldo tlim, ilim vpp 5.0 v/3.3 v 150 ma ldo tlim, ilim vdd3_3 3.3 v 120 ma ldo, pass tlim, ilim vddl drive adj. volt. 40 ma dual pass tlim reset detection vddh, vdd3_3, vddl vddh 5.0 v 400 ma ldo tlim, ilim vref2 5.0 v 100 ma ldo tlim, ilim vref3 5.0 v 100 ma ldo tlim, ilim 16 bit spi control fault rep. por timer sleep 21 22 23 24 25 highspeed can transceiver 20 19 18 10 nf 47 f 10 nf 1.0 f 10 nf 1.0 f 10 nf 1.0 f 10 nf 47 f 17 16 15 14 13 12 11 10 vsen vbat volt. 125 ma tlim, ilim vkam keepalive adj. volt. 60 ma ilim gnd canl cantxd canh canrxd 26 27 28 29 30 31 10 nf 10 nf 22 f 2.6 v 100 f 10 f buck control logic boost vpre q3 mjd31c q2 mjd31c 10 nf 47 f 10 nf vddh 5.0 v canrxd 4244 41 boot highside drive lowside drive oscillator feed forward ramp generator + + + c1 100 f enable sleep 32 33 34 35 36 37 10 k 10 k 10 k 110r 100r vddl 2.6 v 3.3 v 47 f vref1 vpp_en vpp vdd3_3 vdd3_fb vddl_b do sclk di cs /sleep vref3 vref2 vddh 5.0 v 5.0 v 5.0 v 47 k hrt /prereset /hreset /poreset vddl_x vddl_fb 5.0 v 5.0 v/3.3 v 9 wakeup 8 regon 7 vsen 38 39 40 5 vkam 6 vkam_fb 4 vign 3 ka_vbat 1, 2 vbat 4.7 k on off control dp2 dp1 to q3 cf1 cf2 lf1 6.8 h + vbg 11.7 k 40 k cc1 d2 vpre_s vpre vcomp 100 pf inv gnd sw2g sw1 cb 100 nf d1 q1 mtd20n03hdl l1 47 h cc2 1.0 nf rc2 100 k cc3 3.3 nf rc3 430r vpre 5.6 v 22 k 20 k v q3 vkam 2.6 v v bg notes: 1. in this configuration the device can operate with a minimum input voltage vbat of 4.0 v (voltage at 33394 vbat pins) . notes: 2.vddl and vkam are adjustable to support current microprocessor technology (1.25 v to 3.3 v) by means of an external resisto r divider. notes: 3. when the 33394 can transceiver is not used, canl and canh pins can be shorted together. notes: 4. dp1 = reverse battery protection diode. dp2 = load dump protection diode. dp1, dp2 can be ommitted in those applications w hich do not require such protection. 120 r 1.0 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 3 motorola analog integrated circuit device data pin function description (44hsop package) pin no. name description 1 vbat battery supply to ic (external reverse battery protection needed in some applications) 2 vbat battery supply to ic (external reverse battery protection needed in some applications) 3 ka_vbat keep alive supply (with internal protection diode) 4 vign turnon control through ignition switch (with internal protection diode) 5 vkam vddl tracking keep alive memory (standby) supply 6 vkam_fb vkam output feedback 7 vsen switched battery output 8 regon regulator ahold ono input 9 wakeup can wake up event output 10 vref1 vddh tracking linear regulator 1 11 vpp_en vpp enable 12 vpp 5.0 v/ 3.3 v flash memory programming supply, tracking vddh/vdd3_3 13 vdd3_3 3.3 v regulated supply output, base drive for optional external pass transistor 14 vdd3_3fb vdd3_3 output feedback 15 vddl_x vddl optional external pass transistor base drive, operating in boost mode only 16 vddl_b vddl external pass transistor base drive 17 vddl_fb vddl output feedback 18 /prereset open drain /prereset output, occurs 0.7 us prior to /hreset (hardware reset) 19 /hreset open drain / hreset (hardware reset) output 20 /poreset open drain / poreset (power on reset) supervising vkam supply to the microprocessor. 21 canrxd can receive data (dout) 22 cantxd can transmit data (din) 23 gnd ground 24 canl can differential bus drive low line 25 canh can differential bus drive high line 26 hrt hardware reset timer pin (programmed with external capacitor and resistor) 27 /sleep sleep mode & power down control 28 cs spi chip select 29 di spi serial data in 30 sclk spi clock input 31 do spi serial data out 32 vref3 vddh tracking linear regulator 3 33 vref2 vddh tracking linear regulator 2 34 vddh 5.0 v regulated supply output 35 vpre_s switching preregulator output sense 36 vpre switching preregulator output 37 vcomp switching preregulator compensation (error amplifier output) 38 inv switching preregulator error amplifier inverting input 39 gnd ground 40 sw2g external power switch (mosfet) gate drive e boost regulator 41 boot bootstrap capacitor 42 sw1 source of the internal power switch (nchannel mosfet) 43 sw1 source of the internal power switch (nchannel mosfet) 44 sw1 source of the internal power switch (nchannel mosfet) note: the exposed pad of the 44 hsop package is electrically and thermally connected with the ic ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 4 motorola analog integrated circuit device data pin function description (44qfn package) pin no. name description 1 gnd ground 2 sw2g external power switch (mosfet) gate drive e boost reg. 3 boot bootstrap capacitor 4 sw1 source of the internal power switch (nchannel mosfet) 5 sw1 source of the internal power switch (nchannel mosfet) 6 sw1 source of the internal power switch (nchannel mosfet) 7 vbat battery supply to ic (external reverse battery protection needed in some applications) 8 vbat battery supply to ic (external reverse battery protection needed in some applications) 9 ka_vbat keep alive battery supply (with internal protection diode) 10 vign turn on control through ignition switch (with internal protection diode) 11 vkam vddl tracking keep alive memory (standby) supply 12 vkam_fb vkam output feedback 13 vsen switched battery output 14 regon regulator ahold ono input 15 wakeup can wake up event output 16 vref1 vddh tracking linear regulator 1 17 vpp_en vpp enable 18 vpp 5.0 v/ 3.3 v flash memory programming supply, tracking vddh/vdd3_3 19 vdd3_3 3.3 v regulated supply output, base drive for optional external pass transistor 20 vdd3_3fb vdd3_3 output feedback 21 vddl_x vddl optional external pass transistor base drive, operating in boost mode only 22 vddl_b vddl external pass transistor base drive 23 vddl_fb vddl output feedback 24 /prereset open drain /prereset output, occurs 0.7 us prior to /hreset (hardware reset) 25 /hreset open drain / hreset (hardware reset) output 26 /poreset open drain / poreset (power on reset) supervising vkam supply to the microprocessor. 27 canrxd can receive data (dout) 28 cantxd can transmit data (din) 29 gnd ground 30 canl can differential bus drive low line 31 canh can differential bus drive high line 32 hrt hardware reset timer pin (programmed with external capacitor and resistor) 33 /sleep sleep mode & power down control 34 cs spi chip select 35 di spi serial data in 36 sclk spi clock input 37 do spi serial data out 38 vref3 vddh tracking linear regulator 3 39 vref2 vddh tracking linear regulator 2 40 vddh 5.0 v regulated supply output 41 vpre_s switching preregulator output sense 42 vpre switching preregulator output 43 vcomp switching preregulator compensation (error amplifier output) 44 inv switching preregulator error amplifier inverting input note: the exposed pad of the 44 qfn package is electrically and thermally connected with the ic ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 5 motorola analog integrated circuit device data pin function description (54 soicwep package) pin no. name description 1 gnd ground 2 canl can differential bus drive low line 3 canh can differential bus drive high line 4 hrt hardware reset timer pin (programmed with external capacitor and resistor) 5 /sleep sleep mode & power down control 6 n/c no connect 7 cs spi chip select 8 di spi serial data in 9 sclk spi clock input 10 do spi serial data out 11 n/c no connect 12 vref3 vddh tracking linear regulator 3 13 vref2 vddh tracking linear regulator 2 14 vddh 5.0 v regulated supply output 15 vpre_s switching preregulator output sense 16 vpre switching preregulator output 17 vcomp switching preregulator compensation (error amplifier output) 18 inv switching preregulator error amplifier inverting input 19 gnd ground 20 sw2g external power switch (mosfet) gate drive e boost regulator 21 boot bootstrap capacitor 23 sw1 source of the internal power switch (nchannel mosfet) 24 sw1 source of the internal power switch (nchannel mosfet) 25 sw1 source of the internal power switch (nchannel mosfet) 26 sw1 source of the internal power switch (nchannel mosfet) 27 sw1 source of the internal power switch (nchannel mosfet) 28 vbat battery supply to ic (external reverse battery protection needed in some applications) 29 vbat battery supply to ic (external reverse battery protection needed in some applications) 30 vbat battery supply to ic (external reverse battery protection needed in some applications) 31 vbat battery supply to ic (external reverse battery protection needed in some applications) 32 vbat battery supply to ic (external reverse battery protection needed in some applications) 33 ka_vbat keep alive supply (with internal protection diode) 34 n/c no connect 35 vign turnon control through ignition switch (with internal protection diode) 36 vkam vddl tracking keep alive memory (standby) supply 37 vkam_fb vkam output feedback 38 vsen switched battery output 39 regon regulator ahold ono input 40 wakeup can wake up event output 41 vref1 vddh tracking linear regulator 1 42 vpp_en vpp enable 43 vpp 5.0 v/ 3.3 v flash memory programming supply, tracking vddh/vdd3_3 44 vdd3_3 3.3 v regulated supply output, base drive for optional external pass transistor 45 vdd3_3fb vdd3_3 output feedback 46 vddl_x vddl optional external pass transistor base drive, operating in boost mode only 47 vddl_b vddl external pass transistor base drive 48 vddl_fb vddl output feedback 49 n/c no connect 50 /prereset open drain /prereset output, occurs 0.7 us prior to /hreset (hardware reset) 51 /hreset open drain / hreset (hardware reset) output 52 /poreset open drain / poreset (power on reset) supervising vkam supply to the microprocessor. 53 canrxd can receive data (dout) 54 cantxd can transmit data (din) note: the exposed pad of the 54 soicwep package is electrically and thermally connected with the ic ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 6 motorola analog integrated circuit device data 1. maximum ratings (maximum ratings indicate sustained limits beyond which damage to the device may occur. voltage parameters are absolute voltages referenced to ground.) parameter min. max. unit supply voltage (vbat), load dump 0.3 +45 v supply voltage (ka_vbat, vign), load dump 18 +45 v supply voltages (vddh, vpp, vdd3_3, vddl, vkam) 0.3 +5.8 v supply voltages (vref1, vref2, vref3, vsen) 2.0 +18 v canl, canh (0 33394 8 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: buck converter buck converter output voltage, vbat = 7.5v to 18v; i load =500ma vpre 5.4 5.6 5.8 v buck to boost mode threshold voltage (note 1) vbat thd 6.7 v boost to buck mode threshold voltage (note 1) vbat thu 7.2 v nchannel power mosfet sw1 sw1 drainsource breakdown voltage (note 1) bv dss 50 v sw1 continuous drain current id sw1 2.75 a sw1 drainsource current limit isc sw1 2.5 3.0 3.5 a sw1 drainsource onresistance; i d = 1.0 a, vbat = 9.0 v r ds(on) 300 m w error amplifier (design information only) input offset voltage (note 1) v os 20 mv dc open loop gain (note 1) a vol 80 db unity gain bandwidth (note 1) bw 1.5 mhz output voltage swing e high level (note 1) v oh 4.2 v output voltage swing e low level (note 1) v ol 0.4 v output source current (note 1) i out 1.0 ma output sink current (note 1) i out 200 m a ramp generator sawtooth peak voltage (note 1) v osc 3.5 v sawtooth peaktopeak voltage (note 1) v oscpp 3.0 v boost converter external power mosfet gate drive sw2g boost converter output voltage, vbat = 4.5 v to 6.0 v (note 1) vpre 5.9 6.0 6.6 v sw2g output voltage, power mosfet on (note 1) v g vpre v sw2g source continuous current (note 1) i source tbd ma sw2g sink continuous current i sink 200 300 400 ma ac characteristics: buck converter oscillator frequency freq 180 200 220 khz sw1 switch turnon time (note 1) t ton tbd ns sw1 switch turnoff time (note 1) t toff tbd ns sw2g switch turnon time, c gate = pf (note 1) t ton tbd ns sw2g switch turnoff time, c gate = pf (note 1) t toff tbd ns off time (note 1) t off 1.25 m s duty cycle (note 1) d 75 % note: 1. guaranteed by design but not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 9 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: vddh vddh output voltage, i vddh = 400 ma; vddh 4.9 5.0 5.1 v vddh load regulation, vbat = 13.3 v; i vddh = 0 to 400 ma; loadrg vddh 40 40 mv vddh line regulation, vbat = 4.0 v to 26.5 v; i vddh = 400 ma; linerg vddh 20 20 mv vddh drop out voltage, vpre vddh, i vddh = 400 ma; decrease vbat until resets asserted v dov 450 mv vddh output current, vbat = 4.0 v to 26.5 v i vddh 400 ma vddh short circuit current, vddh = 0 v i sc 750 440 ma vddh maximum allowed feedback current (note 1) (power up sequence guaranteed) (note 2) 135 m a vddh reset voltage, range of vddh where resets must remain asserted v vddh_hrst 0.5 4.8 v thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c vdd3_3 vdd3_3 output voltage, i vdd3_3 = 120 ma; vdd3_3 3.21 3.3 3.36 v vdd3_3 load regulation, vbat = 13.3 v; i vdd3_3 = 0 to 120 ma loadrg vdd3 40 40 mv vdd3_3 line regulation, vbat = 4.0v to 26.5v; i vdd3_3 = 120ma linerg vdd3 20 20 mv vdd3_3 drop out voltage, vpre vdd3_3 i vdd3_3 = 120 ma; decrease vbat until resets asserted v dov 2.04 v vdd3_3 output current, vbat = 4.0 v to 26.5 v i vdd3_3 120 ma vdd3_3 short circuit current, vdd3_3 = 0 v i sc 320 130 ma vdd3_3 maximum allowed feedback current (note 1) (power up sequence guaranteed) (note 2) 135 m a vdd3_3 reset voltage range of vdd3_3 where resets must remain asserted v vdd3_hrst 0.5 3.1 v thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c vddl vddl feedback reference voltage, pin vddl_fb i vddl_b = 0 to 40 ma vddl ref 1.242 1.267 1.292 v vddl load regulation, vbat = 13.3 v; i vddl_b = 0 to 40 ma loadrg vddl 1.6 0 % vddl line regulation vbat = 4.0 v to 26.5 v; i vddl_b = 40 ma linerg vddl 0.8 0.8 % vddl drop out voltage, vpre vddl i vddl = 400 ma; vbat decreases until resets asserted v dov 1.3 v vddl reset voltage, (note 1) range of vddl where resets must remain asserted v vddl_hrst 0.5 vddl 5% v vddl susceptibility to feeding back (note 3) (power up sequence guaranteed) vddl ref 0.187 v vddl_b drive output current, vbat = 7.5v to 26.5v i vddl_b 40 ma vddl_b drive short circuit current vddl_b = 0v, vbat = 7.5v to 26.5v isc vddl_b 100 45 ma vddl_x drive output current, vbat = 4.0 v to 6 v i vddl_b 40 ma vddl_x drive short circuit current, vddl_x = 0v, vbat = 4.0v to 6v isc vddl_x 100 45 ma vddl feedback vddl_fb input current, vddl_fb = 5.0 v i vddl_fb 0 2.0 m a note: 1. guaranteed by design but not production tested. 2. maximum allowed current flowing back into the regulator output. 3. voltage fed back into the vddl output, which still guaranties proper power up sequencing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 10 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: vkam vkam feedback reference voltage, pin vkam_fb normal mode (switcher running), i vkam = 0 to 50ma vkam ref 1.242 1.267 1.292 v vkam load regulation, vbat = 13.3 v; i vkam = 0 to 50 ma loadrg vkam 1.6 0 % vkam line regulation, vbat = 4.0 v to 26.5 v; i vkam = 50 ma linerg vkam 0.8 0.8 % vkam tracking to vddl voltage, vddl vkam vbat = 4.0 v to 26.5 v; i vkam = 0 to 50 ma, i vddl = 0 to 400ma vt vkam 1.6 0.8 % vkam feedback voltage e power down mode 3.0 v battery voltage 26.5 v, i vkam = 12 ma vkam 0.675 v vkam reset voltage (/poreset) range of vkam where resets must remain asserted v vkam_hrst 0.5 vkam 5% v vkam output current (normal mode), vbat = 4.0 v to 26.5 v i vkam 50 ma vkam output current (sleep mode and when vbat 4.0 v) i vkam(sleep) 12 ma vkam short circuit current, vkam = 0 v i sc 140 50 ma vkam feedback vkam_fb input current, vkam_fb = 5.0 v i vkam_fb 0 2.0 m a vkam output capacitance required, capacitor initial tolerance 10% 22 100 m f vpp vpp 5.0v output voltage (default), i vpp = 150 ma vpp 5 4.86 5.0 5.12 v vpp 3.3 v output voltage (programmed by spi) i vpp = 150 ma vpp 3 3.22 3.3 3.38 v vpp load regulation, vbat = 13.3 v; i vpp = 0 to 150 ma loadrg vpp 0.8 0.8 % vpp line regulation, vbat = 4.0 v to 26.5 v; i vpp = 150 ma linerg vpp 0.4 0.4 % vpp tracking to vddh voltage, vddh vpp, vbat = 4.0 v to 26.5 v; i vpp = 0 to 150 ma; i vddh = 0 to 400 ma vt vpp 0.8 0.8 % vpp drop out voltage, vpre e vpp (vpp set to default 5.0v) i vpp = 150 ma; decrease vbat until vpp is out of specification (less than 4.86 v) v dov 0.4 v vpp output current, vbat = 4.0 v to 26.5 v i vpp 150 ma vpp short circuit current, vpp = 0 v i sc 360 165 ma thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c note: 1. guaranteed by design but not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 11 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: vref1, 2, 3 vref output voltage, i vref = 100 ma vref 4.86 5.0 5.12 v vref load regulation, vbat = 13.3 v; i vref = 0 to 100 ma loadrg vref 40 40 mv vref line regulation, vbat = 4.0 v to 26.5 v; i vref = 100 ma linerg vref 20 20 mv vref tracking to vddh voltage, vddh vref, vbat = 4.0 v to 26.5 v, i vref = 0 to 100 ma; i vddh = 0 to 400 ma vt vref 40 20 mv vref drop out voltage, vprevref i vref = 100 ma; decrease vbat until vref is out of specification (less than 4.86 v) v dov 0.4 v vref output current, vbat = 4.0 v to 26.5 v i vref 100 ma vref short circuit current, vref = 2.0 v i sc 260 110 ma vref short to battery load current, vbat = 18 v, vref = 18 v istb vref 40 ma vref leakage current, vref disabled, vref = 2.0 v i lkvref 2.0 ma thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c vsen vsen saturation voltage, i vsen = 0 to 125 ma, vbat= 8 to 16 v vsen sat 0.2 v vsen output voltage limit, i vsen = 0 to 125ma, vbat= 16 to 26.5v vsen limit 16 17 21 v vsen short circuit current, vsen = 2.0 v isc vsen 290 140 ma vsen short to battery load current, vbat = 18 v, vsen = 18 v istb vsen 40 ma vsen leakage current, vsen disabled, vsen = 2.0 v i lkvsen 200 m a thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c note: 1. guaranteed by design but not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 12 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: supervisory outputs reset voltage thresholds /hreset to follow /prereset by 0.7 m s vddh reset upper threshold voltage (note 1) 5.2 v vddh reset lower threshold voltage (note 1) 4.8 v vdd3_3 reset upper threshold voltage (note 1) 3.43 v vdd3_3 reset lower threshold voltage (note 1) 3.17 v vddl reset upper threshold voltage (notes 1, 4) 1.35 v vddl reset lower threshold voltage (notes 1, 4) 1.2 v /poreset voltage threshold vkam reset upper threshold voltage (notes 2, 5) 1.35 v vkam reset lower threshold voltage (notes 2, 5) 1.2 v /prereset, /hreset, /poreset open drain maximum voltage (note 3) 7.0 v /prereset, /hreset, /poreset open drain pulldown current, v reset < 0.4 v 1.0 ma /prereset, /hreset, /poreset lowlevel output voltage, iol = 1.0 ma 0.5 v /prereset /hreset /poreset leakage current 15 m a wakeup highlevel output voltage, ioh = 800 m a vddh0.8 v wakeup lowlevel output voltage, iol = 1.6 ma 0.4 v hrt voltage threshold 2.49 2.53 2.57 v hrt sink current 1.0 ma hrt leakage current 5.0 m a hrt saturation voltage, hrt current = 1 ma 0.4 v ac characteristics: supervisory outputs /poreset delay delay time from vkam in regulation and stable to the release of /poreset 7.0 10 15 ms reset delay time time from fault on vddh, vdd3_3, vddl or vkam to reset (/poreset, /prereset) 10 20 50 m s /hreset delay time time from /prereset low to /hreset low 0.5 0.7 1.0 m s vddh, vddl, vref power up sequence max power up sequence time dependent on output load characteristics. (note 3) 800 m s note: 1. vddh, vdd3_3, vddl regulator outputs supervised by /prereset and /hreset. 2. vkam regulator output supervised by /poreset. 3. guaranteed by design but not production tested. 4. measured at the vddl_fb pin. 5. measured at the vkam_fb pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 13 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: can transceiver (bus load canh to canl r l = 60 w ; vdiff = v canh v canl ) can transceiver supply current (dominant), v cantxd = 0v i dd(can) 30 50 70 ma can transceiver supply current (recessive), v cantxd = vddh i dd(can) 2.5 5 10 ma transmitter data input cantxd highlevel input voltage threshold (recessive), vdiff<0.5v v ih 1.4 2.0 v lowlevel input voltage threshold (dominant), vdiff>1.0v v il 0.8 1.4 v highlevel input current, vcantxd = vddh i ih 5 0 +5 m a lowlevel input current, v cantxd = 0v i il 10 15 30 m a cantxd pullup current, v cantxd = 0v to v ih(max) i pu 10 60 m a cantxd input capacitance (note 1) c i(txd) 5 10 pf receiver data output canrxd highlevel output voltage v cantxd = vddh, i canrxd = 0.8 ma v oh vddh 0.8 vddh v lowlevel output voltage, v cantxd = 0, i canrxd = 1.6 ma v ol 0.4 v highlevel output current, v canrxd = 0.7vddh i oh 800 m a lowlevel output current, v canrxd = 0.4v i ol 1.6 ma bus lines canh, canl output voltage canh (recessive) v cantxd = vddh; r l = open v canh(r) 2.0 2.5 3.0 v output voltage canl (recessive) v cantxd = vddh; r l = open v canl(r) 2.0 2.5 3.0 v output current canh (recessive) v cantxd = vddh; v canh , v canl = 2.5v i o(canh)(r) 100 m a output current canl (recessive) v cantxd = vddh; v canh , v canl = 2.5v i o(canl)(r) 100 m a output voltage canh (dominant), v cantxd = 0v v canh(d) 2.75 3.5 4.5 v output voltage canl (dominant), v cantxd = 0v v canl(d) 0.5 1.5 2.25 v differential output voltage (dominant) v canh(d) v canl(d) v cantxd = 0v v odiff(d) 1.5 2.0 3.0 v differential output voltage (recessive) v canh(r) v canl(r) v cantxd = vddh v odiff(r) 0 0.5 v differential input common mode voltage range v cm 2.0 7.0 v differential receiver threshold voltage (recessive) v cantxd = vddh, v canrxd < 0.4v, 2.0v < v cm < 7.0v v rxddiff(th) 0.5 0.75 1.0 v differential receiver input voltage hysteresis v idiff(hys) 0.10 0.2 0.30 v short circuit output current canh v canh = 8.0v, v cantxd = 0v i sc(canh) 70 200 ma short circuit output current canl v canl = vbat = 18v, v cantxd = 0v i sc(canl) 70 200 ma loss of ground e see figure 11. refer to figure 10 for loading considerations. output leakage current canh, v canh = 18v i olkg(canh) 2.0 2.0 ma output leakage current canhl, v canl = 18v i olkg(canl) 2.0 2.0 ma loss of battery e see figure 12. refer to figure 10 for loading considerations. input leakage current canh, v canh = 6.0v i ilkg(canh) 800 800 m a input leakage current canhl, v canl = 6.0v i ilkg(canl) 800 800 m a note: 1. guaranteed by design but not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 14 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: can transceiver (continued) (bus load canh to canl r l = 60 w ; vdiff = v canh v canl ) canh,canl impedance canh common mode input resistance r i(cm)canh 5.0 25 50 k w canl common mode input resistance r i(cm)canl 5.0 25 50 k w canh, canl common mode input resistance mismatch 100(r icanh r i(cm)canl )/[ (r icanh + r i(cm)canl )/2] r i(cm)mcan 3.0 3.0 % differential input resistance r i(dif) 25 50 75 k w canh input capacitance, v cantxd = vddh (note 1) c i(canh) 7.5 20 pf canl input capacitance, v cantxd = vddh (note 1) c i(canl) 7.5 20 pf differential input capacitance, c incanh c incanl , v cantxd = vddh (note 1) c i(candif) 3.75 10 pf thermal shutdown thermal shutdown junction temperature (note 1) ts dis 150 190 c thermal shutdown hysteresis (note 1) ts hys 5.0 20 c ac characteristics: can transceiver timing characteristics see figure 2, cantxd = 250 khz square wave; canh & canl load r l = 60 w differential. delay cantxd to bus active, c l = 3nf t ontxd 50 ns delay cantxd to bus inactive, c l = 10pf t offtxd 80 ns delay cantxd to canrxd, bus active, c l = 3nf t onrxd 120 ns delay cantxd to canrxd, bus inactive, c l = 10pf t offrxd 190 ns note: 1. guaranteed by design but not production tested. vddh (5v) 0.9 v 0.5 v 0.7vddh 0.3vddh cantxd vdiff canrxd tontxd tonrxd tofftxd toffrxd 0 v vddh (5v) 0 v canh (recessive bit) canl (recessive bit) figure 2. can delay timing waveform 2.5 v vdiff canh = 3.5v (dominant bit) canl = 1.5v (dominant bit) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 15 motorola analog integrated circuit device data 3. electrical characteristics (40 c t a +125 c; +4.0 v vbat +26.5 v using the 33394 typical application circuit see figure 1, unless otherwise noted.) characteristic symbol min. typ. max. unit dc characteristics: spi do output high voltage, i oh = 100 m a v oh 4.2 v do output low voltage, i ol = 1.6 ma v ol 0.4 v do tristate leakage current, cs = 0 i dolkg 10 10 m a cs, sclk, di input high voltage v ih 2.7 3.1 3.5 v cs, sclk, di input low voltage v il 1.7 2.1 2.5 v cs, sclk, di input voltage threshold hysteresis v ihys 0.8 1.0 1.2 v cs, sclk, di pulldown current, cs, sclk, di = vddh to v il(min) i spi_pd 10 20 50 m a ac characteristics: spi notes: mpc565 qsmcm/ spi set for cpha = 0 & cpol = 0. *assumes mpc565 sclk rise and fall times of 30 ns, do load = 200pf transfer frequency fop dc 5.00 mhz 1 sclk period tsck 200 ns 2 enable lead time tlead 105 ns 3 enable lag time tlag 50 ns 4 sclk high time* tsckhs 70 ns 5 sclk low time* tsckls 70 ns 6 sdi input setup time tsus 16 ns 7 sdi input hold time ths 20 ns 8 sdo access time ta 75 ns 9 sdo disable time tdis 100 ns 10 sdo output valid time tvs 75 ns 11 sdo output hold time tho 0 ns 12 rise time (design information) (note 1) tro 30 ns 13 fall time (design information) (note 1) tfo 30 ns 14 cs negated time (note 1) tcsn 500 ns note: 1. guaranteed by design but not production tested. figure 3. spi timing diagram 3 14 2 4 1 5 8 10 11 9 67 12 13 cs sclk do di lsb out data msb out don't care lsb in data msb in 20% and 70% of vdd typ. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 16 motorola analog integrated circuit device data 4. functional description the 33394 is an integrated buck regulator/linear supply specifically designed to supply power to the motorola mpc55x/mpc56x microprocessors. a detailed functional description of the buck regulator, linear regulators, power up/down sequences, thermal shutdown protection, can transceiver reset functions and reverse battery function are given below. block diagram of the 33394 is given in figure 1. the 33394 is packaged in a 44 pin hsop, 54 pin soicw and the 44 pin qfn. 4.1. input power source (vbat, ka_vbat & vign) the vbat and ka_vbat pins are the input power source for the 33394. the vbat pins must be externally protected from vehicle level transients greater than +45 v and reverse battery. see typical application diagram in figure 1. the vbat pins directly supply the preregulator switching power supply. all power to the linear regulators (except vkam in the power down mode) is supplied from vbat through the switching regulator. vkam power is supplied through vbat input pins and switching regulator when the 33394 is awake. when the microprocessor is in a power down mode (no vddh or vddl supply), the current requirement on vkam falls to less than 12 ma. during this period the vkam current is supplied from the reverse battery protected ka_vbat input. the ka_vbat supply pin is the power source to the keep alive memory regulator (vkam) in power down mode. power is continuously supplied regardless of the state of the ignition switch (vign input). the ka_vbat input is reverse battery protected but requires external load dump protection (refer to figure 1). the vign pin is used as a control input to the 33394. the regulation circuits will function and draw current from vbat when vign is high (active) or regon is high (active) or on can bus activity (wakeup active). to keep the vign input from floating, a 10k pulldown resistor to gnd should be used. the vign pin has a 3.0 v threshold and 1.0 volt of hysteresis. vign is designed to operate up to +26.5 volt battery while providing reverse battery and +45 volt load dump protection. the input requires esd, and transient protection. see figure 1 for external component required. 4.2. switching regulator functional description a block diagram of the internal switching regulator is shown in figure 4. the switching regulator incorporates circuitry to implement a buck or a buck/boost regulator with additional external components. a high voltage, low r ds(on) power mosfet is included on chip to minimize the external components required to implement a buck regulator. the power mosfet is a sense fet to implement current limit. for low voltage operation, a low side driver is provided that is capable of driving external logic level mosfets. this allows a switching regulator utilizing buck/boost topology to be implemented. two independent control schemes are utilized in the switching regulator. in buck mode, voltage mode pulsewidth modulation (pwm) control is used. the switcher output voltage divided by an internal resistor divider is sensed by an error amplifier and compared with the bandgap reference voltage. the pwm comparator uses the output signal from the error amplifier as the threshold level. the pwm comparator compares the sawtooth voltage from the ramp generator with the output signal from the error amplifier thus creating a pwm signal to the control logic block. the error amplifier inverting input and output are brought out to enable the control loop to be externally compensated. the compensation technique is described in paragraph 5.2.3. buck converter feedback compensation in the application information section . in order to improve line rejection, feed forward is implemented in the ramp generator. the feed forward modifies the ramp slope in proportion to the vbat voltage in a manner to keep the loop gain constant, thus simplifying loop compensation. at startup, a soft start circuit lowers the current limit value to prevent potentially destructive inrush current. in boost mode, pulsefrequency modulation (pfm) control is utilized. the duty cycle is set to 75% and the switching action is stopped either by the boost comparator, sensing the switcher output voltage vpre, or by the current limit circuit when the switching current reaches its predetermined limit value . this control method requires no external components. the selection of the control method is determined by the control logic based on the vbat input voltage. 4.2.1. switching transistor (sw1) the internal switching transistor is an nchannel power mosfet. the r ds(on) of this internal power fet is approximately 0.25 ohm at +125 c. the 33394 has a nominal instantaneous current limit of 3.0 a (well below the saturation current of the mosfet and external surface mounted inductor) in order to supply 1.2 a of current for the linear regulators that are connected to the vpre pin (see figure 1). the input to the drain of the internal nechannel mosfet must be protected by an external series blocking diode, for reverse battery protection (see figure 1). 4.2.2. bootstrap pin (boot) an external bootstrap 0.1 m f capacitor connected between sw1 and the boot pin is used to generate a high voltage supply for the high side driver circuit of the buck controller. the capacitor is pre charged to approximately 10v while the internal fet is off. on switching, the sw1 pin is pulled up to vbat, causing the boot pin to rise to approximately vbat+10v e the highest voltage stress on the 33394. 4.2.3. external mosfet gate drive (sw2g) this is an output for driving an external fet for boost mode operation. due to the fact that the gate drive supply voltage is vpre the external power mosfet should be a logic level device. it also has to have a low r ds(on) for acceptable efficiency. during buck mode, this gate output is held low. 4.2.4. compensation (inv, vcomp) the pwm error amplifier inverting input and output are brought out to allow the loop to be compensated. the recommended compensation network is shown in figure 18 and its bode plot is in figure 19. the use of external compensation components allows optimization of the buck converter control loop for the maximum bandwidth. refer to the paragraph 5.2.3. buck converter feedback compensation in the application information section for further details of the buck controller compensation. 4.2.5. switching regulator output voltage (vpre) the output of the switching regulator is brought into the chip at the vpre pin. this voltage is required for both the switching regulator control and as the supply voltage for all the linear regulators. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 17 motorola analog integrated circuit device data 4.2.6. switching regulator output voltage sense (vpre_s) this is the switching regulator output voltage sense input. the switcher output voltage vpre is divided by an internal resistor divider and compared with the bandgap reference voltage (see figure 4). refer to section 5 application information for detailed description of the switching regulator operation. figure 4. switching regulator block diagram buck & boost control logic current limit soft start + + feed forward ramp generator thermal limit switcher oscillator 200 khz switcher mode enable v bg + pwm comp v bg v bg vpre comp bootstrap vbat + boost comp v bg 1.25 v v bg 1.25 v v bg 1.25 v e/a ls driver hs driver vpre vpre boot sw1 vpre sw2g vpre_s inv vcomp 40 k 11.7 k 4.3. voltage regulator (vddh) the vddh output is a linearly regulated +5.0 +/ 0.10v voltage supply capable of sourcing a maximum of 400 ma steady state current from vpre (+5.6 v) for vbat voltages from +4.0 v to +26.5 v (+45v transient). this regulator incorporates current limit short circuit protection and thermal shut down protection. the voltage output is stable under all load/line conditions. however, the designer must consider ripple and high frequency filtering as well as regulator response, when choosing external components. see table 1 in the applications information section for recommended output capacitor parameters. note : backfeeding into the vddh output can cause problems during the power up sequence. refer to the electrical characteristics vddh regulator section for the maximum allowed backfed current into the vddh output. 4.4. tracking voltage regulator (vpp) this linearly regulated +5.0 v/+3.3 v (spi selectable) voltage supply is capable of sourcing 150 ma of steady state current from vpre (+5.6 v) for vbat voltage from +4.0 v to +26.5 v (up to +45v transient). it tracks the vddh or vdd3_3 output, and incorporates current limit short circuit protection and over temperature shut down protection. this output is intended for flash memory programming and includes a dedicated enable pin (vpp_en). the regulator enable can also be controlled through the spi interface but requires both the vpp_en pin and the spi bit (en_vpp bit) to be high to enable. the selection of tracking vddh or vdd3_3 is controlled by the vpp_v bit in the spi. logic a1o selects vddh (default), logic a0o selects vdd3_3. the voltage output is stable under all load/line conditions. however, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. see table 1 for recommended output capacitor parameters. the vpp tracking regulator should not be used in parallel with the vddh regulator, because this arrangement can corrupt the proper power sequencing of the ic. 4.5. tracking voltage regulator (vrefn) the outputs of the vref1, vref2, vref3 linear regulators are 100 ma at +5.0 v. they track the vddh output. the power supplies are designed to supply power to sensors that are located external to the module. these regulators may be enabled or disabled via the spi, which also provides fault reporting for these regulators. they are protected for short to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 18 motorola analog integrated circuit device data battery (+18 v) and short to 2.0 v. precautions must be taken to protect the vref pins from exposure to transients. see table 1 for recommended output capacitor parameters. 4.5.1. vref over temperature latch off feature if either the vref1, vref2 or vref3 outputs is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150 c to +190 c. the output transistor remains off until the locally sensed temperature is 5 c to 20 c. below the trip off temperature. the output(s) will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. if one of these outputs goes into overetemperature shutdown, it will not impact the operation of any of the other outputs (assuming that no other package thermal or vpre current limit specifications are violated). fault information is reported through the spi communication interface (see figure 8). 4.6. voltage regulator (vdd3_3) this linearly regulated +3.3 v +/0.06 v voltage supply is capable of sourcing 120 ma of steady state current from vpre (+5.6 v) for vbat voltage from +4.0 v to +26.5 v (+45v transient). this regulator incorporates current limit short circuit protection and thermal protection. when no external pass transistor is used the vdd3_3 and the vdd3_3fb pins must be shorted together e see figure 22. the current capability of the vdd3_3 output can be increased by means of an external pass transistor e see figure 1. when the external pass transistor is used the vdd3_3 internal short circuit current limit does not provide the short circuit protection. the voltage output is stable under all load/line conditions. however, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. see table 1 in the applications information section for recommended output capacitor parameters. note : backfeeding into the vdd3_3 output can cause problems during the power up sequence. refer to the electrical characteristics vdd3_3 regulator section for the maximum allowed backfed current into the vdd3_3 output. 4.7. voltage regulator (vddl) the output voltage of the vddl linear regulator is adjustable by means of an external resistor divider. this linearly regulated +/2% core voltage supply uses an external pass transistor and is capable of sourcing 40 ma base drive current typically (see application circuit, figure 1) of steady state current. the collector of the external npn pass transistor is connected to vpre (+5.6 v) for a vbat voltage from +7.5 v to +26.5 v (+45v transient). the voltage output is stable under all load/line conditions. however, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. also, the dynamic load characteristics of the microprocessor, relative to cpu clock frequency changes must be considered. an additional external pass transistor, for vddl regulation in the boost mode, can be added between protected battery voltage (see figure 1) and vddl, with its base driven by vddl_x. in that arrangement the 33394's core voltage supply operates over the whole input voltage range vbat = +4.0 v to +26.5 v (up to +45v transient). see table 1 in the applications information section for recommended output capacitor parameters. notes: 1. the use of an external pass device allows the power dissipation of the 33394 to be reduced by approximately 50% and thereby allows the use of a thermally efficient package such as an hsop 44 or qfn 44. the base drive control signal (vddl_b) is provided by on chip circuitry. the regulated output voltage sense signal is fed back into the on chip differential amplifier through pin vddl_fb. the collector of this external pass device should be connected to vpre to minimize power dissipation and adequately supply 400 ma. proper thermal mounting considerations must be accounted for in the pcb design. 2. backfeeding into the vddl output can cause problems during the power up sequence. refer to the electrical characteristics vddl regulator section for the maximum allowed backfed current into the vddl output. 4.8. keepalive/standby supply (vkam) this linearly regulated keep alive memory voltage supply tracks the vddl (+1.25 v to +3.3 v) core voltage, and is capable of sourcing 50 ma of steady state current from vpre during normal microprocessor operation and 12 ma through ka_vbat pin during standby/sleep mode. the vkam regulator output incorporates a current limit short circuit protection. the output requires a specific range of capacitor values to be stable under all load/line conditions. see table 1 in the applications information section for recommended output capacitor parameters. note : the source current for the vkam supply output depends on the sleep/wake state of the 33394. 4.9. switched battery output (vsen) this is a saturated switch output, which tracks the vbat and is capable of sourcing 125 ma of steady state current from vbat. this regulator will track the voltage vbat to less than 200 mv, and its output voltage is clamped at +17 v. the gate voltage of the internal nechannel mosfet is provided by a charge pump from vbat. there is an internal gatetosource voltage clamp. this regulator is short circuit protected and has independent overetemperature protection. if this output is shorted and goes into thermal shutdown, the normal operation of all other voltage outputs is not impacted. this output is controlled by the spi vsen bit. note: a short to vbat on vref1, vref2, vref3 or vsen will not result in additional current being drawn from the battery under normal (+8 v to +18 v) voltage levels. under jumpstart condition (vbat = +26.5 v) and during load dump condition, the device will survive this condition, but additional current may be drawn from the battery. 4.9.1. vsen over temperature latch off feature if the vsen output is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150 c to +190 c. the output transistor remains off until the locally sensed temperature drops 5 c to 20 c below f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 19 motorola analog integrated circuit device data the tripoff temperature. the output will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. if the vsen output goes into overetemperature shutdown, it does not impact the operation of any of the other outputs (assuming that no other package thermal or vpre current limit specifications are violated). fault information is reported through the spi communication interface (see figure 8). 4.10. resets to microprocessor /poreset power on reset, /prereset e pre reset, /hreset hardware reset. all the reset pins are open drain `active low' outputs, capable of sinking 1.0 ma current and able to withstand +7.0 v. see figure 1 and figure 20 for recommended pullup resistor values and their connection. the /poreset pin is pulled up to the vkam voltage by a pull up resistor. it is connected to the microprocessor power on reset (por) pin, and is normally high. during initial battery connect the /poreset is held to ground by the 33394. after the vkam supply is in regulation and an internal 10 ms timer has expired, the /poreset is released. if vkam goes out of regulation the device will first pull the /poreset and /prereset followed by a 0.7 m s delay then /hreset. by /hreset low vddh, vdd3_3 and vddl will start a power down sequence. when the fault is removed a standard power up sequence is initiated. the vkam linear regulator output must be out of regulation for greater than 20 m s before /porerset and /prereset (with /hreset 0.7 m s delayed) are pulled low. if a fault occurs on vkam in the keyoff mode (when the vign is off) and the fault is then removed the vkam will regulate but /poreset will not be released until keyon (asserting vign pin) allows the 10 ms timer to run. the reset signals (/prereset, /hreset) are not asserted when the 33394 enters sleep mode by asserting the /sleep pin. when exiting out of sleep mode the 33394 asserts the resets (/prereset, /hreset) during the power up sequence. the /prereset and /hreset pins are pulled up to the vkam (see figure 1) or to vddl (see figure 20). refer to section 5. application information , paragraph 5.3. selecting pullup resistors for detailed description of these two connection scenarios. the 33394 monitors the main supply voltages vddh, vdd3_3 and vddl. if any of these voltages falls out of regulation limits the /prereset will be pulled down followed by the /hreset after 0.7 m s delay, and the power down sequence will be initiated. there are several different scenarios how to connect the /prereset and /hreset pins to the microprocessor. typically the /prereset pin will be connected to the irq0 pin of the microprocessor, and the /hreset to the microprocessor /hreset pin (see figure 5). the vddh, vdd3_3 and vddl linear regulator outputs must be out of regulation for greater than 20 m s before /prereset (with /hreset 0.7 m s delayed) are pulled low. 4.11. hardware reset timer (hrt) the hrt pin is used to set the delay between vddh, vdd3_3 and vddl active and stable and the release of the /hreset and /prereset outputs. an external resistor and capacitor is used to program the timer. to minimize quiescent current during power down modes, the rc timer current should be drawn from one of the vdd supplies (see figure 1). the threshold on the hrt pin has zero temperature coefficient and is set at 2.5 v. 4.12. power up/down sequencing the 33394 power up sequence is specifically designed to meet the power up and power down requirements of the mpc565 microprocessor. the mpc565 processor requires that vddh remain within 3.1 volts of vddl during power up and can not lag vddl by more than 0.5 volts. this condition is met by the 33394 regardless of load impedance. it is critical to note that the 33394 under normal conditions is designed to supply vkam prior to the power up sequence on vddh, vdd3_3 and vddl. during power up and power down sequencing /prereset and /hreset are held low. power up and power down sequencing is implemented in six steps. during this process the reference voltage for vddh, vdd3_3 and vddl is ramped up in six steps. minimum power up/down time is dependent on the internal clock and is 800 m s. maximum power up/down time is also dependent on load impedance. during the power up/down cycle, voltage level requirements for each step of vddh, vdd3_3 and vddl must be met before the supply may advance to the next voltage level. hence vddh and vddl will remain within the 3.1/0.5 v window. figure 6 illustrates a typical power up and down sequence. 4.13. regulator enable function (regon) this feature allows the microcontroller to select the delayed shut down of the 33394 device. it holds off the activation of the reset signals, to the microcontroller, after the vign signal has transitioned and signals the request to shutdown the vddh, vdd3_3, vddl, vsen and the vrefn supplies. this allows the microcontroller to delay a variable amount of time, after sensing that the vign signal has transitioned and signaled the request to shutdown the regulated supplies. this time can be used to store data to eprom memory, schedule an orderly shutdown of peripherals, etc. the microcontroller can then drive the regon signal, to the 33394, to the low logic state, to turn off the regulators (except for the vkam supply). 4.14. regulator shutdown function (/sleep) this feature allows for an external control element (e.g. microprocessor) to shut down the 33394 regulators, even if the vign signal (or regon) is active, by asserting the /sleep pin from high to low (falling edge transition). in this case the 33394 initiates the power down sequence, but the reset signals (/prereset, /hreset) are not asserted. this allows the microprocessor to continue to execute code when it is supplied only from the keep alive supply vkam. when the microprocessor exits sleep state by pulling /sleep pin high the resets (/prereset, /hreset) are asserted during the power up sequence. the /sleep pin has an internal pull down, therefore when its functionality is not used this pin can be either pulled up to vkam, vbat, pulled down to ground or left open. the /sleep pin should not be pulled up to vddh. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 20 motorola analog integrated circuit device data figure 5. 33394 timing diagram vddh = 5.0v vdd3_3 = 3.3v* vddl = 2.6v vkam = 2.6v 2.6v 2.6v 2.6v 0.7 s 0.7 s 0.7 s hrt delay hrt delay hrt delay vddh, vdda, vflash5 kapwr, vddsram1,2,3 vddrtc poreset irq0 hreset mpc56x vddh vdd3_3 vddl vign vkam /poreset /prereset /hreset 10ms 3 2 1 4 5 6 8 10 11 9 7 33394 output supply input nvddl, qvddl, vdd, vddsyn, vddf 5.0v 2.6v * vdd3_3 = 3.3v (not used by mpc56x) 1 module connected to the battery, vkam starts to regulate, /poreset is released after vkam is in regulation for 10 ms. 2 vign is applied, 33394 starts power up sequence. 3 vddh, vdd3_3, vddl are stable and in regulation before /prereset and /hreset are released (with a hrt delay programmable by an external capacitor and resistor, hrt pin). 4 any of vddh, vdd3_3, vddl voltages out of regulation initiate /prereset asserted. power down sequence initiated. 5 /hreset is asserted 0.7 s after /prereset 6 when fault is removed and vddh, vdd3_3, vddl are in regulation, the /prereset and /hreset outputs are released (with an hrt delay). 7 when vkam goes out of regulation limits (4% below its nominal value), /poreset, /prereset and /hreset (/hreset with 0.7 s delay) are asserted see note 1. 8 33394 initiates power down sequence. 9 fault on vkam removed, the 33394 initiates the start up sequence. 10 when vddh, vdd3_3, vddl are in regulation again, the /prereset and /hreset outputs are released (with an hrt delay). 11 /poreset is released with a 10 ms delay after the fault on vkam was removed. figure 6. 33394 power up/down sequence vddh = 5.0 v vdd3_3 = 3.3 v vddl = 2.6 v* power up sequence power down sequence 0 v *note: vddl = 2.6 v for mpc565 less than 3.1 v * vkam voltage level for mpc55x devices is 3.3 v and for mpc56x devices is 2.6 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 21 motorola analog integrated circuit device data 4.15. spi interface to microcontroller (serial peripheral interface) the pins specified for this function are: di (data input), do (data output), cs (chip select) and sclk. refer to figure 3 for the 33394 spi timing information. the delay, which is needed from cs leading edge active to the first sclk leading edge transition (0 to 1) is approximately 125 ns. the sclk rate is a maximum of 5.0 mhz. the spi function will provide control of such 33394 features as vrefn regulator turn on/off, vrefn fault reporting and can wake up feature activation. refer to figure 7 & figure 8 for the data and status bit assignments for the 16 bit spi data word exchange. 4.15.1. cs (chip select) pin the system mcu selects the 33394 to be communicated with through the use of the cs pin. whenever the pin is in a logic high state, data can be transferred from the mcu to the 33394 and vice versa. clockedein data from the mcu is transferred to the 33394 shift register and latched in on the falling edge of the cs signal. on the rising edge of the cs signal, output status information is transferred from the output status register into the device's shift register. whenever the cs pin goes to a logic high state, the do pin output is enabled allowing information to be transferred from the 33394 to the mcu. to avoid any spurious data, it is essential that the transition of the cs signal occur only when sclk is in a logic low state. 4.15.2. sclk (system clock) pin the shift clock pin (sclk) clocks the internal shift registers of the 33394. the serial input (di) data is latched into the input shift register on the rising edge of the sclk. the serial output pin (do) shifts data information out of the shift register also on the rising edge of the sclk signal. it is essential that the sclk pin be in a logic low state whenever the chip select pin (cs) makes any transition. for this reason, it is recommended though not necessary, that the sclk pin is commanded to a low logic state as long as the device is not accessed (cs in logic low state). when cs is in a logic low state, any signal at the sclk and di pin is ignored and the do is triestated (high impedance). 4.15.3. di (data input) pin the di pin is used for serial data input. this information is latched into the input register on the rising edge of sclk. a logic high state present on di will program a specific function (see figure 7 for the data bits assignments for the 16 bit spi data word exchange.). the change will happen with the falling edge of the cs signal. to program the specific function of the 33394 a 16 bit serial stream of data is required to be entered into the di pin starting with lsb. for each rising edge of the sclk while cs is logic high, a data bit instruction is loaded into the shift register per the data bit di state. the shift register is full after 16 bits of information have been entered. to preserve data integrity, care should be taken to not transition di as sclk transitions from a low to high logic state. 4.15.4. do (data output) pin the serial output (do) pin is the output from the shift register. the do pin remains triestate until the cs pin goes to a logic high state. see figure 8 for the status bits assignments for the 16bit spi data word exchange. the cs positive transition will make lsb status available on do pin. each successive positive sclk will make the next bit status available. the di/do shifting of data follows a firsteinefirsteout protocol with both input and output words transferring the least significant bit (lsb) first. 33394 spi registers: serial input data/control default value 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name bit definitions: bit 15 to 8 = 0 default value 1 1 1 1 1 1 1 1 bit 7 6 5 4 3 2 1 0 (lsb) name wkup can_en vpp_v en_vpp vsen vref3 vref2 vref1 bit definitions: bit 7 e wkup: wakeup activation. wkup = 1: wakeup pin will signal can bus activity bit 6 e can_en: enables can receiver, will draw small current during power off bit 5 e vpp_v: set vpp reference to 5v (1) or 3.3v (0), default is 5v bit 4 e en_vpp: used to turn the vpp regulator off and on from the mcu bit 3 e vsen: used to turn the vsen regulator off and on from the mcu bit 2 e vref3: used to turn the vref3 regulator off and on from the mcu bit 1 e vref2: used to turn the vref2 regulator off and on from the mcu bit 0 e vref1: used to turn the vref1 regulator off and on from the mcu figure 7. spi input data/ control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 22 motorola analog integrated circuit device data 33394 spi registers: serial output data/status default value 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name bit definitions: bit 15 to 8 = 0 default value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 (lsb) name vsent vref3t vref2t vref1t vseni vref3i vref2i vref1i bit definitions: bit 7 e vsent: will be set (1), if a thermal limit occurred since last spi data transfer bit 6 e vref3t: will be set (1), if a thermal limit occurred since last spi data transfer bit 5 e vref2t: will be set (1), if a thermal limit occurred since last spi data transfer bit 4 e vref1t: will be set (1), if a thermal limit occurred since last spi data transfer bit 3 e vseni: will be set (1), if a current limit condition exists bit 2 e vref3i: will be set (1), if a current limit condition exists bit 1 e vref2i: will be set (1), if a current limit condition exists bit 0 e vref1i: will be set (1), if a current limit condition exists notes: # individual thermal limit latch will clear on the trailing edge of the spi cs signal figure 8. spi output data/ status register 4.16. can transceiver the can protocol is defined in terms of 'dominant' and 'recessive' bits. when the digital input (cantxd) is a logic o0o (negated level, dominant bit), canh goes to +3.5 v (nominal) and canl goes to +1.5 v (nominal). the digital output will also be negated. when the digital input is logic o1o (asserted level, recessive bit), canh and canl are set to +2.5 v (nominal). the corresponding digital output is also asserted. 4.16.1. can network topology there are two 120 w (only two), terminations between the canh and canl outputs. the majority of the time, the module controller will contain one of the terminations. the other termination should be as close to the other oendo of the can bus as possible. the termination provides a total of 60 w differential resistive impedance for generation of the voltage difference between canh and canl. current flows out of canh, through the termination, and then through canl and back to ground. the can bus is not defined in terms of the bus capacitance. a filter capacitor of 220 pf to 470 pf may be required. the maximum capacitive load on the can bus is then 15 nf (not a lumped capacitance but distributed through the network cabling). refer to figure 9. max : 31 remotes canh canl pcm vehicle term. 120 120 470 pf* 470 pf* 470 pf* 470 pf* *optional common mode choke 2.2 mh figure 9. can load characteristics 4.16.2. can transceiver functional description a block diagram of the can transceiver is shown in figure 10 . a summary of the network topology is shown in figure 9. the transceiver has wake up capability controlled by the state of the spi bit wkup. this allows 33394 to enter a low power mode and be awakened by can bus activity. when activity is sensed on the can bus pins, the 33394 will perform a power up sequence and will provide the microprocessor with indication (wakeup pin high) that wake up occurred from a can message. the 33394 may be placed back in low quiescent mode by pulling the /sleep pin from high to low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 23 motorola analog integrated circuit device data the wakeup function can be disabled through spi by setting the wkup bit to 0. the can transceiver of the 33394 is designed for communications speeds up to 1.0 mbps. the use of a common mode choke may be required in some applications. when the 33394 can transceiver physical interface is not used in the system design, the can bus driver pins canh and canl should be shorted together. 4.16.3. canh canh is an output driver stage that sources current on the canh output. it's output follows canl, but in the opposite polarity. the output is short circuit protected. in the event that battery or ground is lost to the module, the canh transmitter's output stage is disabled. 4.16.4. canl canl is an output driver stage that sinks current on the canl output. the sink type output is short circuit protected. in the event that battery or ground is lost to the module, the canl transmitter's output stage is disabled. 4.16.5. cantxd cantxd input comes from the microcontroller and drives that state of the can bus pins, canh and canl. a logic `0' input drives the outputs to a differential (dominant) voltage, where the canh output is +3.5 v and the canl output is +1.5 v. a logic `1' input drives the outputs to their idle (recessive) state, where the canh and canl outputs are +2.5 v. an internal pullup to vddh shall guarantee a logic o1o input level if this input is left open. on powerup, or in the event of a thermal shutdown, this input must be toggled high and then low to clear the thermal fault latch. the faulted can bus output(s) will remain disabled until the thermal fault latch is cleared. the can bus data rate is determined by the data rate of cantxd. 4.16.6. canrxd this is a cmos compatible output used to send data from the can bus pins, canh and canl, to the microprocessor. when the voltage differential between canh and canl is under the differential input voltage threshold (recessive state), canrxd is logic `1'. when the voltage differential between canh and canl is over the voltage threshold (dominant state), canrxd is logic `0'. in standby mode, input voltage threshold remains the same. there is a minimum of 0.1 v of hysteresis between the high and low (and vice versa) transition points. figure 10. can transceiver block diagram + + 25 k 25 k 5 k 5 k 2.5 v 10 m a 0.8 2.0 v 0.5 1.0 v canrxd awake can_en vddh overtemp sense & hysteresis vddh can_en canl canh cantxd canrxd complimentary high/low side drivers w/ current limit 4.16.7. can over temperature latch off feature if the canh or canl output is shorted to ground or battery for any duration of time, an over temperature shut down circuit disables the output stage. the output stage remains latched off until the cantxd input is toggled from a logic '1' to a logic '0' to clear the over temperature shutdown latch. thermal shutdown does not impact the remaining functionality of the ic. 4.16.8. can loss of assembly ground the definition of a loss of ground condition at the device level is that all pins of the ic (excluding transmitter outputs) will see very low impedance to vbat. the loss of ground is shown on the module level in figure 11. the nomenclature is suited to a test environment. in the application, a loss of ground condition results in all i/o pins floating to battery voltage. in this condition, the can bus must not source enough current to corrupt the bus. 4.16.9. can loss of assembly battery the loss of battery condition at the ic level is that the power input pins of the ic see infinite impedance to the battery supply voltage (depending upon the application) but there is some undefined impedance looking from these pins to ground. in this condition, the can bus must not sink enough current to corrupt the bus. refer to figure 12. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 24 motorola analog integrated circuit device data power oak vbat gnd canl canh icanl icanh vdd3_3 vddh vign vddl + + 43 2v 43 68 51 2v figure 11. can loss of ground test circuit battery 16 v figure 12. can loss of battery test circuit power oak vbat gnd canl canh icanl icanh battery vdd3_3 vddh vign vddl + + 43 +6v 43 68 51 +6v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 25 motorola analog integrated circuit device data 5. application information this section provides information on external components that are required by the 33394. the ic is designed to operate in an automotive environment. conducted immunity and radiated emissions requirements have been addressed during the design. however, the ic requires some external protection. protection is required for all pins connected directly to battery. the module designer should use an mov or another transient voltage suppressor in all cases, when the load dump transition exceeds + 45 volts with respect to ground. protection should also include a reverse battery protection diode (or relay) and input filter. this is required to protect the 33394 from esd and +/ 300v ignition transients. typical configurations are shown in figure 1. outputs and inputs connected directly to connector pins require module level esd protection. 5.1. selecting components for linear regulators the output capacitor of the linear regulator serves two different purposes. it maintains the linear regulator loop stability, and it provides an energy reservoir to supply current during very fast load transients. this is especially true when supplying highly modulated loads like microcontrollers and other highspeed digital circuits. due to the limited bandwidth of the linear regulators, the output capacitor is selected to limit the ripple voltage caused by these abrupt changes in the load current. during the fast load current transients, the linear regulator output capacitor alone controls the initial output voltage deviation. hence, the output capacitor's equivalent series resistance (esr) is the most critical parameter. the outputs, which do not experience such severe conditions (the vref e.g.), use the output capacitor mainly for stability purpose, and therefore its capacitance value can be significantly smaller. the typical output capacitor parameters are: c = 1.0 m f; esr = 2.0 ohms. when a ceramic 1 m f capacitor is used, the esr can be provided by a discrete serial resistor (see figure 20). the following example shows how to determine the output capacitance for a heavily loaded output supplying digital circuits. 5.1.1. selecting the output capacitor example: the output capacitance must be selected to provide sufficiently low esr. the selected capacitor must have an adequate voltage, temperature and ripple current rating for the particular application. in order to calculate the proper output capacitor parameters, several assumptions will be made. 1) during the very fast load current transients, the linear regulator can not supply the required current fast enough, and therefore for a certain time the entire load current is supplied by the output capacitor. 2) the capacitor's equivalent series inductance (esl) is neglected. these assumptions can greatly simplify the calculations, and are reasonable for most of practical applications. then the esr of the output capacitor has to satisfy the following condition: esr v o i o where: d vo is the maximum allowed linear regulator voltage drop caused by the load current transient. d io is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. in this example the vddh output with the 400 ma load step is considered with the maximum voltage drop of 100mv. this gives the output capacitor's maximum esr value of: esr 100 mv 400 ma 250 m this level of esr requires a relatively large capacitance. in order to maintain the linear regulator stability and to satisfy large load current steps requirements the solid tantalum capacitor 100 m f/10v with esr = 200 m w . one device that meets these requirements is the tpsc107k010s020 tantalum capacitor from the avx corporation. v esr esr i o 200 m 400 ma 80 mv in the next step, the voltage drop associated with the capacitance can be calculated: v c i o t c 0.4 a 5 s 100 f 20 mv where: c is the output capacitance. t is the linear regulator response time. d i o is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. assuming that the capacitor esl is negligible, the total voltage drop in the voltage regulator output caused by the current fast transient can be calculated as: v total v esr v c 80 mv 20 mv 100 mv a ceramic capacitor with capacitance value 10nf should be placed in parallel to provide filtering for the high frequency transients caused by the switching regulator. properly sized decoupling ceramic capacitor close to the microprocessor supply pin should be used as well. table 1 shows the suggested output capacitors for the 33394 ic linear regulator outputs. other factors to consider when selecting output capacitors include key off timing for memory retention. though the vkam is not a heavily loaded output, the vkam output capacitor has to have a sufficiently large capacitance value to supply current to the microcontroller for a certain time after battery voltage is disconnected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 26 motorola analog integrated circuit device data table 1. linear regulator output capacitor examples output smd tantalum value/rating part n. (avx corp.) vddh 100uf/10v tpsc107k010s0200 vpp 33uf/10v tpsb336k010s0650 vdd3_3 68uf/6.3v tpsc686k006s0200 vddl 100uf/6.3v tpsc107k006s0150 vrefx 10uf/16v thjb106k016s vkam* 100uf/6.3v tpsc107k006s0150 5.2. switching regulator operation the 33394 switching regulator circuit consists of two basic switching converter topologies. one is the typical voltage mode pwm stepdown or buck regulator, which provides preregulated vpre voltage (+5.6 v) during normal operating conditions. during cold startup, when the car battery is weak, the input voltage for the 33394 can fall below the lower operating limit of the stepdown converter. under such conditions, the stepup or boost converter provides the required value of the vpre voltage. the following paragraphs describe the basic principles of the two converters operation. buck mode one switching cycle of the stepdown converter operation has two distinct parts: the power switch on state and the off state. when the power switch is on, one inductor terminal is connected to the input voltage vin, and the other inductor terminal is the output voltage v o . during this part of the switching period the rectifier (catch diode) is back biased, and the current ramps up through the inductor to the output: i l(on) (v in v o ) t on l where: t on is the ontime of the power switch. v in is the input voltage. v o is the output voltage. i l(on) is the inductor current during the ontime. l is the inductance of the inductor l. during the on time, current ramping through the inductor stores energy in the inductor core. during the off time of the power switch, the input voltage source vin is disconnected from the circuit. the energy stored in the core forces current to continue to flow in the same direction, the rectifier is forward biased and the inductor input voltage is clamped one forward diode drop below ground. the inductor current during the off time is: i l(off) (v o v fwd ) t off l where: t off is the offtime of the power switch. i l(off) is the inductor current during the off time. v fwrd is forward voltage drop across the rectifier. during the steady state operation i l(on) = i l(off) = d i l , and v in /v o = d where: d is the duty cycle, and d = t on /t. t is switching period, t = 1/f. f is the frequency of operation. two relations give the ripple voltage in the output capacitor c o . the first describes ripple voltage caused by current variation upon the output capacitance c o : vpp co i l 8co f the other is caused by current variations over the output capacitor equivalent series resistance esr: vpp esr i l r esr practically, the esr contributes predominantly to the buck converter ripple voltage: v ppesr >>v ppco the inductor peak current can be calculated as follows: ipk l i o 1 2 i l where: i o is the average output current. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 27 motorola analog integrated circuit device data figure 13. basic buck converter operation and its waveforms i q i l i d d q v in r load v o + + c o l v in r load + + c o l power switch on i load v out i lo v d(fwd) r load + + c o power switch off i load v out i lo i o i l i q i d v d v co i l t on t off t v fwd t boost mode the operation of the boost converter also consists of two parts, when the power switch is on and off. when the power switch turns on, the input voltage source is placed directly across the inductor, and the current ramps up linearly through the inductor as described by: i l(on) v in t on l where: t on is the ontime of the power switch. v in is the input voltage. i l(on) is the inductor current during the ontime. l is the inductance of the inductor l. the current ramping across the inductor stores energy within the core material. in order to maintain steadystate operation, the amount of energy stored during each switching cycle, times the frequency of operation must be higher (to cover the losses) than the power demands of the load: p sto 1 2 li 2 pk f p out when the power switch turns off again, the inductor voltage flies back above the input voltage and is clamped by the forward biased rectifier at the output voltage. the current ramps down through the inductor to the output until the new on time begins or, in case of discontinuous mode of operation, until the energy stored in the inductor core drops to zero. i l(off) (v o v in ) t off l where: t off is the offtime of the power switch. v o is the output voltage. during the steady state operation i l(on) = i l(off) = d i l , and d v o v in v o where: d is the duty cycle, and d = t on /t. t is switching period, t = 1/f. f is the frequency of operation. the ripple voltage of the boost converter can be described as: vpp co i o c o (v o v in ) v o f where: v ppco is the ripple caused by output current. the portion of the output ripple voltage caused by the esr of the output capacitor is: vpp esr (i o v o v in 1 2 i l ) r esr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 28 motorola analog integrated circuit device data where i o is the average output current. the inductor peak current is given by the following equation: ipk l i o v o v in 1 2 i l figure 14. basic boost converter operation and its waveforms i l i d i q q l v in r load v o + + c o d v in r load + + c o l power switch on i load v out v in r load + + c o power switch off i off v out i l i o i l i d i q v q v co i l t on t off t i on i load t 5.2.1. switching regulator component selection the selection of the external inductor l2 and capacitor c2 values (see figure 15) is a compromise between the two modes of operation of the switching regulator, the pre regulated voltage vpre and the dropout voltage of the linear regulators. ideal equations describing the peakepeak inductor current ripple, peakepeak output voltage ripple and peak inductor current are shown below. since the switching regulator will work mostly in the buck mode, the inductor and the switcher input and output capacitor were selected for optimum buck controller performance, but also taking into account the restriction placed by adopting the boost converter as well. figure 15. 33394 switcher topology i l v rl v fwd1 d 1 l v in r load v o + + c o r l q 2 v rds(on) r ds(on) i q q 1 esr d 2 v fwd2 the following example shows a procedure for determining the component values. the vpre output is set to regulate to 5.6 v and the linear regulators require a minimum of 0.4 v dropout voltage. this leaves a 0.2 v window for the peaketopeak output voltage ripple. assuming the following conditions: v in (typ) = 13.5 v i o = 1.2 vpre = 5.6 v (+6 v in the boost mode) f = 200 khz v fwd1 = v fwd2 = 0.5 v maximum allowed output voltage ripple in the buck mode v pp(max) = 0.2 v/2 = 0.1 v (to allow for process and temperature variations). 5.2.1.1. selecting the inductor in order to select the proper inductance value, the inductor ripple current d i l has to be determined. the usual ratio of d i l to output current i o is: d i l = 0.3 i o as described in the previous section , and taking into account the 33394 switcher topology (see figure 15), the inductor ripple current can be estimated as: i l (v in v o v fwd2 ) l v o v fwd2 v in f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 29 motorola analog integrated circuit device data after substitution, the calculated inductance value is l = 45 m h, which gives 47 m h standard component value. the peakto peak ripple current value is: d i l = 0.345 a. the peak inductor current is given by: i lpk = 0.5 d i l + i o = 0.5x0.345 + 1.2 = 1.37[a] the inductor saturation current is given by the upper value of the 33394 internal switch current limit i lim(max) = 3.0 a. considering also the inductor serial resistance, these requirements are met, for example by the po250.473t inductor from pulse engineering, inc. 5.2.1.2. selecting the catch diode d 1 the rectifier d 1 current capability has to be greater than calculated average current value. the maximum reverse voltage stress placed upon this rectifier d 1 is given by maximum input voltage (maximum transient battery voltage). these requirements are met, for example by the hsm350 (3 a, 50 v) schottky diode from microsemi, inc. 5.2.1.3. selecting the output capacitor the output capacitor c o should be a low esr part, therefore the 100 m f tantalum capacitor with 80 m w esr was chosen. from the formula for calculating the ripple voltage: v ppesr = d i l x r esr = 0.345 x 0.08 = 28 [mv] one device that meets both, the low esr, and the temperature stability requirements is, for example, the tpsv107k020r0085 tantalum capacitor from avx corp. boost converter power capability the boost converter with selected components has to be able to deliver the required power. due to the nature of this noncompensated pfm control technique, the boost converter output ripple voltage is higher than if it utilized a typical pwm control method. therefore the switcher output voltage level is set higher than in the buck mode (in the boost mode vpre = +6 v), in order to maintain a sufficient dropout voltage for the 5volt linear regulators (vddh, vrefs) and to avoid unwanted resets to the microcontroller. the most stringent conditions for the 33394 boost converter occur with the lowest input voltage: v in(min) = 3.5 v i o = 0.8 a vpre = +6 v f = 200 khz v fwd1 = v fwd2 = 0.5 v d = 0.75, duty cycle is fixed at 75% in boost mode figure 16. 33394 switcher topology boost mode i l v res l v in r load v o + + c o r d q 2 esr d 2 v fwd2 i q i l i lim i 01 i 02 i l1 < i l2 tt i l1 i l2 l1 > l2 i o1 > i o2 the input voltage drop associated with the resistance of the internal switch q1 and inductor series resistance can be estimated as: v d i pk(min) r d 2.5 a 0.35 0.875 v where: v d is the voltage dissipated on the major parasitic resistances, r dson of the internal power switch and inductor series resistance r l. for the worst case conditions: r d = r dson(max) + r l = 0.25 + 0.1 = 0.35[ w ] i pk(min) is the minimum internal power switch current limit value. then the equation for calculating d i l can be modified as follows: i l v in v d l [ (v o v fwd2 ) (v in v d ) ] d (v o v fwd2 ) f 3.5 0.875 47 10 6 [ (6 0.5) (3.5 0.875) ] 0.75 (6 0.5) 0.2 10 6 125[ma] then the maximum average input current can be calculated as: i inave i pk(min) 1 2 i l 2.5 0.125 2 2.43[a] finally, the boost converter power capability has to be higher than the required output power or: p in(max) p out where p in(max) is the boost converter maximum input power: h is the boost converter efficiency, in our case h is estimated to be h = 85%, and includes switching losses of the external power switch q2 (mosfet) inductor and capacitors ac losses, and output rectifier d2 (schottky) switching losses. p out is the boost converter output power, which includes power loss of the output rectifier d2: p out (v o v fwd2 ) i o (6 0.5) 0.8 5.2[w] p in (v in v d ) i inave (3.5 0.875) 2.43 0.85 5.42[w] as can be seen, the boost converter input power capability meets the required criteria. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 30 motorola analog integrated circuit device data 5.2.1.4. selecting the power mosfet q2 the boost converter maximum output voltage plus the voltage drop across the output schottky rectifier d2 gives the mosfet's maximum drainsource voltage stress: bv dsq2 >v o +v fwd2 = 6 v+0.5 v, as can be seen, the breakdown voltage parameter is not critical. the more important in our case is the q2 current handling capability. the external power mosfet has to withstand higher currents than the upper current limit of the 33394: i dq2 >3a in order to keep the power dissipation of the 33394 boost converter to its minimum, a very low r dson power mosfet has to be selected. moreover, due to the fact that the 33394 external mosfet gate driver is supplied from vpre, in order to assure proper switching of q2 a logic level device has to be selected. last but not least, the q2 package has to suitable for the harsh automotive environment with low thermal resistance. these requirements are met, for example by the mtd20n03hdl power mosfet from on semiconductor. 5.2.1.5. selecting the boost converter output rectifier d2 criteria similar to that of selecting the power mosfet was used to select the boost converter output rectifier. its reverse breakdown voltage is not a critical parameter: v rd2 >v o =6 v the d2 rectifier has to withstand higher peak current than is the 33394 internal switch upper current limit i lim(max) . the most important parameter is its forward voltage drop, which has to be minimal. this parameter is also crucial for the proper 33394 switcher functionality, and especially for proper transition between the buck and boost modes. finally, its switching speed, forward and reverse recovery parameters play a significant role when selecting the output rectifier d2. these requirements are met, for example by the hsm350 schottky rectifier from microsemi, inc. 5.2.2. input filter selection since the switcher will work in the boost mode only during cold crank condition, the 33394 emc (electromagnetic compatibility) performance is not of concern during this mode of operation. therefore, only the buck mode of operation is important for selecting the appropriate input filter. for the buck converter topology (see figure 13) the low impedance 3rd order filter (c3, l2, c4 and c26 in the application schematic diagram figure 20) offers a good solution. it can be seen from the buck converter current waveforms that comparatively high current pulses are drawn from the converter's input source. the filter inductance must be kept minimal and the capacitor, which is placed right next to the power switch, must be sized large enough to provide sufficient energy reservoir for proper switcher operation. the esr of this input capacitor combination c4, c26 has to be sufficiently low to reduce the switching ripple of the switcher input node vbat. there are three main reasons to keep the voltage ripple of the vbat pin at its minimum. first, it is the emc (electromagnetic compatibility) performance of the switcher in the normal operating mode (buck mode). second, it allows a smooth transition between the boost and buck mode of operation. third, it helps to avoid entering an undervoltage condition too early. a practical way to achieve sufficiently low esr of the switcher input capacitor, even at low temperature extremes, is to use several high value ceramic capacitors in parallel with a large electrolytic capacitor. these capacitors should be physically placed as close to the vbat pins as possible. 5.2.3. buck converter feedback compensation a typical control loop of the buck regulator is shown in figure 17. the loop consists of a power processing block e the modulator in series with an errordetecting block e the error (feedback) amplifier. in principle, a portion of the output voltage (vpre of the 33394 switcher) is compared to a reference voltage (v bg ) in the error amplifier and the difference is amplified and inverted and used as a control input for the modulator to keep the controlled variable (output voltage vpre) constant. figure 17. the buck converter control loop + + z in z f reference voltage error feedback amplifier modulator v out to load ramp pwm signal v in gain block (modulator) feedback block g h v out v in + v out /v in = g/(1 + gh) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 31 motorola analog integrated circuit device data figure 18. error amplifier twopoletwozero compensation network + c2 r2 c1 c3 r1 r3 r ref e/a vcomp vpre_s u1 the process of determining the right compensation components starts with analysis of the open loop (modulator) transfer function, which has to be determined and plotted into the bode plot (see figure 19). the modulator dc gain can be determined as follows: a dc v in v e where v e is the maximum change of the error amplifier voltage to change the duty cycle from 0 to 100 percent (v e = 2.6 v at vbat =14 v). as can be seen from figure 19, the buck converter modulator transfer function has a double complex pole caused by the output lc filter. its corner frequency can be calculated as: f p(lc) 1 2 lc o this double pole exhibits a e40db per decade rolloff and a e180 degree phase shift. another point of interest in the modulator's transfer function is the zero caused by the esr of the output capacitor c o and the capacitance of the output capacitor itself: f z(esr) 1 2 r esr c o the esr zero causes +20db per decade gain increase, and +90 degree phase shift. once the open loop transfer function is determined, the appropriate compensation can be applied in order to obtain the required closed loop cross over frequency and phase margin (~60 degree) e refer to figure 18 and figure 19. figure 19 shows the 33394 switching regulator modulator gainphase plot, e/a gainphase plot, closed loop gainphase plot, and the e/a compensation circuit. the frequency f xo is the required crossover frequency of the buck regulator. in order to achieve the best performance (the highest bandwidth) and stability of the voltagemode controlled buck pwm regulator the twopoletwozero type of compensation was selected e see figure 19 for the compensated error amplifier bode plot, and figure 18 for the compensation network. the two compensating zeros and their positive phase shift (2 x +90 degree) associated with this type of compensation can counteract the negative phase shift caused by the double pole of the modulator's output filter. figure 19. bode plot of the buck regulator a 1 100 k 10 k 1000 100 10 11 m 60 40 20 0 20 40 60 8 0 f (hz) gain (db) 360 270 180 90 0 90 phase (deg) 100 k 10 k 1000 100 10 11 m f (hz) modulator closed loop (overall) error amplifier modulator closed loop (overall) error amplifier f p1 f p2 a 2 f z(esr) f z2 f z1 f p(lc) if xo the frequency of the compensating poles and zeros can be calculated from the following expressions: f z1 1 2 r 2 c 2 f z2 1 2 (r 1 r 3 )c 3 1 2 r 1 c 3 f p1 1 2 r 3 c 3 f p2 c 1 c 2 2 r 2 c 1 c 2 1 2 r 2 c 1 and the required absolute gain is: a 1 r 2 r 1 a 2 r 2 (r 1 r 3 ) r 1 r 3 r 2 r 3 refer to application schematic diagram (figure 20) and table 2 for the 33394 switcher component values. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 32 motorola analog integrated circuit device data table 2. part number (figure 18) application diagram part number (figure 1) component value r1 33394 internal resistor 39.6k w r2 r2 100k w r3 r1 430 w c1 c6 100pf c2 c7 1.0nf c3 c5 3.3nf 5.3. selecting pullup resistors all the resets (/poreset, /prereset and /hreset) are open drain outputs, which can sink a maximum of 1 ma drain current. this determines the pullup resistor minimum value. vkam should be used as the pullup source for the /poreset output. /poreset is pulled low only during initial battery connect or when vkam is below 2.5 volts (for vddl = 2.6 v). to select the /prereset and /hreset pullup resistor connections, consider current draw during sleep modes. for example, the pull up resistor on /prereset and /hreset should receive its source from vddl, if the sleep mode or low power mode of the module is initiated primarily by the state of the vign pin. refer to figure 20 for recommended pullup resistor values. another way to connect the /prereset and /hreset pullup resistors is to connect them to the vkam output together with the /poreset pullup resistor (see figure 1). this is the preferable solution when the sleep or low power mode is initiated primarily by the microprocessor. in that case, when the 33394 is shut down by pulling the /sleep pin down, all three resets (/poreset, /prereset and /hreset) stay high. since they are pulledup to the supply voltage (vkam) they draw no current from the vkam and the module quiescent current is minimized. 5.4. selecting hardware reset timer components the hrt input sets the delay time from vddh, vdd3_3 and vddl stable to the release of /prereset and /hreset. when sizing the delay time the module design engineer must consider capacitor leakage, printed board leakage and hrt pin leakage. resistor selection should be low enough to make the leakage currents negligible. the hardware reset (/hreset) delay can be calculated as follows: delay time: t d rc ln[ ( v b v sat ) v th ( v b v sat ) ] where r is the hrt timer pullup resistor, c is the hrt timer capacitor v b is the pullup voltage, v th is the hrt timer threshold voltage (v th = 2.5v nominal value), v sat is the saturation voltage of the internal pulldown transistor. if the hrt timer pullup resistor is connected to vddh (see figure 1) and the resistor value is 47 k , therefore the v sat can be neglected, the formula for calculating the time delay can be simplified to: t d 0.7 rc 5.5. selecting the vkam resistor divider the vkam linear regulator output voltage is divided by an external resistor divider and compared with the bandgap reference voltage (v bg ) in the input of the vkam error amplifier. the resistor divider can be designed according to the following formula: v kam v kamref 1 r upper r lower v kamref = 1.267 v where v kamref is the bandgap reference voltage. since the vkam feedback pin (vkam_fb) input current is only a few na, the resistor value can be selected sufficiently high in order to minimize the quiescent current of the module. see figure 20 for the vkam resistor divider recommended values. 5.6. selecting the vddl resistor divider the vddl regulator resistor divider is designed according to the same formula as described in the paragraph above (see figure 20). v ddl v ddlref 1 r upper r lower where v ddlref = 1.267 v nonetheless, the actual resistor values should be chosen several decades lower than in the previous example. this is due to the fact that the vddl linear regulator needs to be preloaded by a minimum of 10 ma current in order to guarantee stable operation. see figure 20 for the vddl resistor divider recommended values. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 33 motorola analog integrated circuit device data figure 20. 33394 application circuit schematic diagram vbat +battery jp1 1 2 vddh sw1 dip2 vpp_en ign vign r14 4.7k r3 4.7k c28 10nf c29 1.0uf/50v c3 1.0uf/50v d2 murs320t3 l2 6.8uh q3 12 + c4 100uf/35v vbat 1.0uf/50v c26 + vkam c23 10nf c24 22uf r4 22k r6 20k vref1 c8 10nf c9 1.0uf r19 2.0r vpp + c12 10nf c13 10uf +3.3v + c21 10nf c22 10uf r9 4.7k r10 4.7k r11 4.7k r12 4.7k 37 36 35 34 do sclk di cs vkam /prereset /hreset u1 d1 20bq030 l1 47uh 12 r1 q1 mmsf3300r2 d3 ss25 c1 100nf r13 18r 430r + c5 3.3nf c2 100uf/16v c6 100pf c7 1.0nf vbat vbat vbat vbat ka_vbat n/c vign vkam vkam_fb vsen regon wakeup vref1 vpp_en vpp vdd3_3 vdd3_3fb vddl_x vddl_b vddl_fb n/c /prereset /hreset /poreset canrxd cantxd sw1 sw1 sw1 sw1 sw1 n/c boot sw2g gnd inv vcomp vpre vpre_s vddh vref2 vref3 n/c do sclk di cs n/c /sleep hrt canh canl gnd vsen regon wakeup vpp_en vddl_x vddl_b vddl_fb canrxd cantxd /poreset r16 10k r17 10k r18 10k canh canl c25 * r8 120r r15 47k c18 1.0uf c16 1.0uf vddh vref3 r20 2.0r r21 2.0r c17 10nf c14 1.0uf c15 10nf vref2 c10 47uf c11 10nf vddh + vpre r22 100k boot vpre_s /sleep 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 34 35 36 37 MC33394dwb vpre + vddl_b vddl_x vddl vddl_fb vddl = 2.6v r5 110r c20 47uf c15 10nf q3 q3 mjd31c q2 mjd31c r7 100r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 con/34 j1 +battery gnd +battery gnd +battery gnd +battery gnd vkam /sleep vpp wakeup vsen ign +3.3v regon /poreset /prereset canh /hreset canl canrxd vref2 cantxd vref1 cs vref3 di vpp_en sclk vddh do vddl gnd *notes: 1. d2 is a protection diode against reverse battery fault condition. in those applications, which do not require this type of protection, diode d2 can be ommitted. notes: 2. capacitors c25, c27 are optional and may be used for can tranceiver evaluation. * c27 * c30 10nf table 3. 33394 evaluation board performance parameter value (t a = 25 c, vin = 14v) line regulation (vin = 5.2v to 26.5v) load regulation (vin = 14 v) v [mv] load [ma] [mv] load [ma] v [mv] load [ma] vddh 5.028 400 10 400 18 0 to 400 vpp 5.026 150 10 150 5 0 to 150 vref1 5.023 100 8 100 8 0 to 100 vref2 5.022 100 8 100 10 0 to 100 vref3 5.021 100 6 100 11 0 to 100 vdd3_3 3.307 120 5 120 7 0 to 120 vddl 2.667 400 5 400 10 0 to 400 vkam 2.638 60 2 60 14 0 to 60 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 34 motorola analog integrated circuit device data table 4. 33394dwb evaluation board bill of material item qty. part designator value/ rating part number/ manufacturer 1 1 c1 100nf/16v, ceramic x7r any manufacturer 2 1 c2 100 m f/20v tpsv107k020r0085, avx corp. 3 3 c3,c26,c29 1.0 m f/50v c1812c105k5ractr, kemet 4 1 c4 100 m f/35v uub1v101mnr1gs, nichicon 5 1 c5 3.3nf, ceramic x7r any manufacturer 6 1 c6 100pf, ceramic x7r any manufacturer 7 1 c7 1.0nf, ceramic x7r any manufacturer 8 10 c8,c11,c12,c15,c17,c19,c21,c23,c28,c30 10nf, ceramic x7r any manufacturer 9 4 c9,c14,c16,c18 1.0 m f, ceramic x7r any manufacturer 10 2 c20,c10 47 m f/10v, tantalum tpsc476k010r0350, avx corp. 11 1 c13 10 m f/16v, tantalum tpsb106k016r0800, avx corp. 12 1 c22 10 m f/6.3v, tantalum tpsa106k006r1500, avx corp. 13 1 c24 22 m f/6.3v, tantalum tpsa226k006r0900, avx corp. 14 2 c25,c27 470pf, ceramic x7r any manufacturer 15 1 d1 30v/2a schottky 20bq030, international rectifier 16 1 d2 200v/3a diode murs320t3, on semiconductor 17 1 d3 50v/2a schottky ss25, general semiconductor 18 1 jp1 2pin, 0.2 (5.1mm) terminal block 19 1 j1 34pin, 0.1 x 0.1 pcb header connector 20 1 l1 47 m h p0250.473t, pulse engineering 21 1 l2 6.8 m h p0751.682t, pulse engineering 22 1 q1 30v/11.5a, mosfet mmsf3300r2, on semiconductor 23 2 q2,q3 100v/3a, bjt mjd31c, on semiconductor 24 1 r1 430r, resistor 0805 any manufacturer 25 1 r2 100k, resistor 0805 any manufacturer 26 6 r3,r9,r10,r11,r12,r14 4.7k, resistor 0805 any manufacturer 27 1 r4 22k, resistor 0805, 1% any manufacturer 28 1 r5 110r, resistor 0805, 1% any manufacturer 29 1 r6 20k, resistor 0805, 1% any manufacturer 30 1 r7 100r, resistor 0805, 1% any manufacturer 31 1 r8 120r, resistor 0805 any manufacturer 32 1 r13 18r, resistor 0805 any manufacturer 33 1 r15 47k, resistor 0805 any manufacturer 34 3 r16,r17,r18 10k, resistor 0805 any manufacturer 35 3 r19,r20,r21 2.0r, resistor 0805 any manufacturer 36 1 sw1 2position dip switch bd02, c&k components 37 1 tp1 test point, 0.038 240333, farnell 38 1 u1 integrated circuit 33394dwb/ motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 35 motorola analog integrated circuit device data figure 21. 33394 application circuit with increased 3.3v output current capability vkam_fb vsen regon wakeup vref1 vpp_en vpp vdd3_3 vdd3_3fb vddl_x vddl_b inv vcomp vpre vpre_s vddh vref2 vref3 do sclk di cs vddl_fb /prereset /hreset /poreset canrxd cantxd gnd canl canh hrt /sleep vkam vign ka_vbat vbat vbat sw1 sw1 sw1 boot sw2g gnd pc33394fc 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 11 10 9 8 7 6 5 4 3 2 1 u1 r4 22 k c22 47 f +3.3v c21 10 nf c9 1.0 f c13 33 f c12 10 nf c8 10 nf c18 r15 47 k vddh vkam r16 10 k r17 10 k r18 10 k vpre q2 mjd31c c23 10 nf c24 100 f c1 100 nf c28 10 nf c16 1.0 f c17 10 nf c10 47 f c14 c15 10 nf c11 10 nf 1.0 f vddh vref2 vref3 c5 c30 33 f/16 v optional output filter 2 1 l3 3.3 nf r1 430r mtd20n03hdl q1 20bq030 d1 ss25 d3 2 1 l1 47 h r13 18r c19 10 nf c20 100 f vpre q4 vddl_x vddl_b r7 100r r5 110r vddl_fb q4 mjd31c q3 mjd31c vddl 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j1 con/34 r6 20 k c6 100 pf c7 1.0 nf r2 100 k c29 1.0 f/ 50 v r14 4.7k +battery vign vpre c2 100 f/ 20 v +battery gnd +battery gnd +battery gnd +battery gnd vkam /sleep vpp wakeup vsen ign +3.3v regon /pdreset /prereset canh /hreset canl canrxd vref2 cantxd vref1 cs vref3 di vpp_en sclk vddh do vddl gnd 34 35 36 37 r9 4.7 k do r10 4.7 k sclk r11 4.7 k di r12 4.7 k cs c3 murs320t3 q4 2 1 l2 6.8 h d2 c4 c26 1.0 f/50 v 100 f/ 35 v 1.0 f/ 50 v vddl r19 10r vbat vpre_s 2.6v vkam 5.0v @ 100ma vref1 5.0v @ 400 ma 5.0v @ 100 ma 5.0v @ 100 ma 2.6v @ 400 ma * r3 4.7 k jp1 1 2 vddh sw1 dip2 vpp_en *notes: 1. d2 is a protection diode against reverse battery fault condition. in those applications, which do not require this type of protection, diode d2 can be ommitted. notes: 2. capacitors c25, c27 are optional and may be used for can tranceiver evaluation. c25 * 120r c27 * 5.0v @ 150ma vpp 1.0 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 36 motorola analog integrated circuit device data table 5. 33394fc evaluation board bill of material item qty. part designator value/ rating part number/ manufacturer 1 1 c1 100nf/16v, ceramic x7r any manufacturer 2 1 c2 100 m f/20v tpsv107k020r0085, avx corp. 3 3 c3,c26,c29 1.0 m f/50v c1812c105k5ractr, kemet 4 1 c4 100 m f/35v uub1v101mnr1gs, nichicon 5 1 c5 1.5nf, ceramic x7r any manufacturer 6 1 c6 100pf, ceramic x7r any manufacturer 7 1 c7 1.0nf, ceramic x7r any manufacturer 8 9 c8,c11,c12,c15,c17,c19,c21,c23,c28 10nf, ceramic x7r any manufacturer 9 1 c18 1.0 m f, ceramic x7r any manufacturer 10 3 c9,c14,c16 1.0 m f/35v tantalum tpsa105k035r3000, avx corp. 11 2 c10,c22 47 m f/10v tantalum tpsc476k010r0350, avx corp. 12 1 c13 33 m f/10v tantalum tpsb336k010r0500, avx corp. 13 1 c20 100 m f/6.3v tantalum tpsc107k006r0150, avx corp. 14 1 c24 22 m f/6.3v, tantalum tpsa226k006r0900, avx corp. 15 2 c27,c25 470pf, ceramic x7r any manufacturer 16 1 c30 33 m f/16v tpsc336k016r0300, avx corp. 17 1 d1 30v/ 2a schottky 20bq030, international rectifier 18 1 d2 200v/3a diode murs320t3, on semiconductor 19 1 d3 ss25 ss25, general semiconductor 20 1 jp1 2pin, 0.2 (5.1mm) terminal block 21 1 j1 34pin, 0.1 x 0.1 pcb header connector 22 1 l1 47 m h p0250.473t, pulse engineering 23 1 l2 6.8 m h p0751.682t, pulse engineering 24 1 l3 ferrite bead hf30acc575032/ tdk 25 1 q1 30v/20a mosfet mtd20n03hdl, on semiconductor 26 3 q2,q3,q4 100v/3a bjt mjd31c, on semiconductor 27 1 r1 680r, resistor 0805 any manufacturer 28 1 r2 100k, resistor 0805 any manufacturer 29 6 r3,r9,r10,r11,r12,r14 4.7k, resistor 0805 any manufacturer 30 1 r4 22k, resistor 0805, 1% any manufacturer 31 1 r5 110r, resistor 0805, 1% any manufacturer 32 1 r6 20k, resistor 0805, 1% any manufacturer 33 1 r7 100r, resistor 0805, 1% any manufacturer 34 1 r8 120r, resistor 0805 any manufacturer 35 1 r13 18r, resistor 0805 any manufacturer 36 1 r15 47k, resistor 0805 any manufacturer 37 3 r16,r17,r18 10k, resistor 0805 any manufacturer 38 1 r19 10r, resistor 0805 any manufacturer 39 1 sw1 2position dip switch bd02, c&k components 40 1 tp1 test point 240333, farnell 41 1 u1 integrated circuit MC33394dwb/ motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 37 motorola analog integrated circuit device data figure 22. 33394 buckonly application vbat vbat ka_vbat vign vkam vkam_fb vsen regon wakeup vref1 vpp_en vpp vdd3_3 vdd3_3fb vddl_x vddl_b vddl_fb /prereset /hreset /poreset canrxd cantxd sw1 sw1 sw1 boot sw2g gnd inv vcomp vpre vpre_s vddh vref2 vref3 do sclk di cs /sleep hrt canh canl gnd 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + + + + + + + + + + vddh vddh /poreset /hreset /prereset vkam vpre vddh = 5v @ 400ma vref2 = 5v @ 100ma vref3 = 5v @ 100ma vref1 = 5v @ 100ma vpp = 5v @ 150ma vkam = 2.6v @ 60ma vpre = 5.6v on off input voltage +7v to +26.5v s1 vddl = 2.6v @ 600ma 3.3v @ 120ma c1 100 m f c5 10nf c6 10nf c7 47 m f c8 10nf c9 1.0 m f c16 10nf c17 47 m f c10 10nf c11 47 m f c12 10nf c13 100 m f r6 10k r7 10k r8 10k c18 1.0 m f c19 10nf c15 10nf c14 100 m f c21 10nf c20 1.0 m f ct 1.0 m f cf1 100pf cf2 1nf cf3 3.3nf cb 100nf c2 100 m f r4 22r r3 20r r2 22k r1 20k r5 4.7k q1 mjd44h11 rt 47k rf2 100k rf3 430r l1 47 m f d1 mbrs340t pc33394 60r bav99 330nf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 38 motorola analog integrated circuit device data figure 23. 33394 flyback converter provides symmetrical voltages vbat vbat ka_vbat vign vkam vkam_fb vsen regon wakeup vref1 vpp_en vpp vdd3_3 vdd3_3fb vddl_x vddl_b vddl_fb /prereset /hreset /poreset canrxd cantxd sw1 sw1 sw1 boot sw2g gnd inv vcomp vpre vpre_s vddh vref2 vref3 do sclk di cs /sleep hrt canh canl gnd 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + + + + + + + + + + vddh vddh /poreset /hreset /prereset vkam vpre vddh = 5v @ 400ma vref2 = 5v @ 100ma vref3 = 5v @ 100ma vref1 = 5v @ 100ma vpp = 5v @ 150ma vkam = 2.6v @ 60ma vpre = 5.6v on off input voltage +10v to +26.5v s1 vddl = 2.6v @ 400ma 3.3v @ 120ma c1 100 m f c5 10nf c6 10nf c7 47 m f c8 10nf c9 1.0 m f c16 10nf c17 47 m f c10 10nf c11 47 m f c12 10nf c13 100 m f r6 10k r7 10k r8 10k c18 1.0 m f c19 10nf c15 10nf c14 100 m f c21 10nf c20 1.0 m f ct 1.0 m f cf1 100pf cf2 1nf cf3 3.3nf cb 100nf c2 100 m f r4 22r r3 20r r2 22k r1 20k r5 4.7k q1 mjd31c rt 47k rf2 100k rf3 430r d1 mbrs340t pc33394 +12v @ 100ma + + 12v @ 100ma c23 47 m f c22 47 m f d3 d3 t1 60r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 39 motorola analog integrated circuit device data package dimensions dh suffix 44lead hsop plastic package case 129101 issue o seating plane datum plane bottom view a x 45 e1 e d h e 42x b m bbb c 44 23 22 1 e2 d2 d1 e3 ???? ???? ???? a2 section ww b c1 b1 c e4 a m aaa c exposed heatsink area a b c h pin one id 22x y gauge plane detail y (1.600) l w w bbb c l1 a1 0.325 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane h. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums a and b to be determined at datum plane h. 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. dim min max millimeters a 3.000 3.400 a1 0.025 0.125 a2 2.900 3.100 d 15.800 16.000 d1 11.700 12.600 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 6.400 7.300 e4 2.700 2.900 l 0.840 1.100 l1 0.350 bsc b 0.220 0.350 b1 0.220 0.320 c 0.230 0.320 c1 0.230 0.280 e 0.650 bsc h 0.800 0 8 aaa 0.200 bbb 0.100 e5 1.000 d3 1.000 d3 4x e5 4x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 40 motorola analog integrated circuit device data package dimensions fc suffix 44lead qfn plastic package case 131001 issue d n pin 1 index area exposed die attach pad 6.55 34 11 1 44 6.85 44x 0.23 g 9 b c 0.1 2x 2x c 0.1 a 9 33 23 22 12 0.65 m 0.1 c m 0.05 c a b 44x 0.75 c 0.1 a b c 0.1 a b m m view mm notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. the complete jedec designator for this package is: hfpqfpn. 4. corner chamfer may not be present. dimensions of optional features are for reference only. 5. coplanarity applies to leads, corner leads and die attach pad. 6. for anvil singulated qfn packages, maximum draft angle is 12 . 40x detail m pin 1 identifier 1.0 1.00 0.05 c 0.1 c 0.05 c seating plane 5 detail g view rotated 90 clockwise (0.65) (0.325) 0.8 0.75 0.00 6.55 6.85 0.50 0.37 (3.53) 4 preferred corner configuration detail n (0.25) 4 detail n corner configuration option 0.60 0.60 detail m preferred backside pin 1 index detail t detail t preferred backside pin 1 index (90 ) 2x detail m backside pin 1 index option 0.065 44x (45 ) 0.015 2x 0.39 0.31 0.24 0.24 0.1 0.0 3.4 0.475 0.425 3.3 backside pin 1 index 0.25 0.15 r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 41 motorola analog integrated circuit device data package dimensions dwb suffix 54lead soicwep plastic package case 137701 issue b notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums b and c to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.46 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead shall not less than 0.07 mm. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1 mm and 0.3 mm from the lead tip. 9. the package top may be smaller than the package bottom. this dimension is determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. c l 17.8 7.4 1 27 28 54 0.10 a 2.35 seating plane 0.9 section bb 0.65 r0.08 min b a (0.29) 0.38 0.30 (0.25) ???? ???? ???? plating base metal section aa rotated 90 clockwise 8 0.25 0.22 9 5 0.13 m c ab 6 a c 7.6 18.0 9 4 10.3 5.15 a 54x 52x 2.65 0.3 a 2x 27 tips b c bb 0.1 0.0 0.5 0 8 0 0.25 gauge plane min pin 1 index c c (1.43) 6.6 5.9 0.30 c ab 4.8 4.3 0.30 c ab view cc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 42 motorola analog integrated circuit device data notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 43 motorola analog integrated circuit device data notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33394 44 motorola analog integrated circuit device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. motorola, inc. is an equal opportunity/a ffirmative action employer. motorola and the logo are registered in the us patent & trademark office. all other product or service names are the prop erty of their respective owners. motorola, inc. 2001. how to reach us: usa / europe / locations not listed : motorola literature distribution; p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 japan : motorola japan ltd.; sps, technical information center, 3201, minamiaz abu. minatoku, tokyo 1068573 japan. 8 1334403569 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong ko ng. 85226668334 technical information center: 18005216274 home page : http://www.motorola.com/semiconductors/ MC33394/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
Price & Availability of MC33394
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |